1. Field of the Invention
The present invention is generally directed to a method and system for measuring terminal compatibility and alignment. More specifically, the present invention is directed to a method and system of reading separate chip layout files and assessing their compatibility, in terms of such considerations as the geometry, interconnection, signal, and power therebetween, during a verification stage before actual fabrication.
2. Description of the Related Art
In Integrated Circuit (IC) design, it is often desirable to combine separate chips or dies into a single interconnected stacked-chip package. Generally each separate microchip, chip, or die (used interchangeably herein) typically goes through many stages of verification to ensure proper functionality. Before a chip is fabricated, a computer readable representation including physical dimensions of component parts and various other defining data are stored as a chip layout file. While the chip layout file may already have been extensively formally verified, no tools presently exist to accurately and efficiently verify compatibility between chips to be stacked and interconnected in a sufficiently automated manner.
In Electronic Design Automation (EDA), specifically checking for inter-die connectivity of micro-bumps/ball bumps/bumps/μ-bumps/terminals/bump pads/ solder bumps/bump metal (used interchangeably herein) and Through-Silicon Vias (TSVs) involving two or more dies requires very time consuming and error prone manual checking/visual inspection. Presently, when manufacturers attempt to check inter-die connectivity they typically print out a large floor plan of a circuit or a chip design and then print out another interfacing design and try to scale and align the two. A painstaking visual inspection of each and every terminal on both chips is then manually performed.
The process of visually inspecting and searching for bumps that do not align, are differently shaped/sized, or may represent differing signals is very tedious. Designers have to manually inspect and visually correlate the respective floor plan of the given layouts while cross-referencing spreadsheets, net lists, and label lists for their defining features and properties.
This approach is not very practical as many errors are often made and alignment problems may be missed. Unfortunately, no automated tool is available to effectively aid in this inspection. In fact, EDA tools heretofore known are without sufficient measures to deal with but one chip design database or chip layout at a time. Presently available tools cannot concurrently evaluate multiple separate and distinct chip layout databases and reliably asses the necessary aspects of connectivity therebetween.
The current practice of rendering the separate chip layout designs and incorporating bump pad text of signal and power mapping files, then visually inspecting each and every micro-bump is a very inefficient, error prone, and labor-intensive manner of performing such a verification.
If a problem was found during this manual/visual inspection, the designers would have to go back, modify designs, and iterate through this visual check over and over again which compounds the inefficiency of the present approach. Consequently, time delays, budget overruns, and inefficiencies are introduced into the overall manufacturing process.
There is therefore a need for a method and system for automatically verifying chip compatibility for stacked multi-chip implementation that doesn't rely on manual human visual inspection of each individual bump element.